This invention generally relates to protective layer in semiconductor devices and more particularly to formation of a self aligned capping layer over a metal filled semiconductor feature.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI. The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) have difficulty achieving conformal coatings and adequate step coverages in filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating (electrodeposition) or electroless plating, which methods have previously been limited to the fabrication of patterns on circuit boards, are now emerging as preferable methods for filling metal interconnects structures such as via openings and trench line openings on semiconductor devices. Typically, electroplating uses a suspension of positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate, as a source of electrons, to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer and within etched features to provide an electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface is electroplated with an appropriate metal, for example, aluminum or copper.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multi layer device. Metal interconnect lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and metal interconnect lines are selectively interconnected in order to form the necessary electrical connections.
In forming a damascene structure, via openings and trench line openings are etched into one or more insulating layers and are back-filled with metal, for example copper. The insulating layers (IMD layers) are typically a low-k (low dielectric constant) insulating material which reduces signal delay times caused by parasitic capacitance. The process by which via openings (holes) and trench lines are selectively etched into the insulating layers is typically a photolithographic masking process, followed by a reactive ion etch (RIE) process, both of which are commonly known in the art.
In filling the via openings and trench line openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer, for example Tantalum nitride or titanium nitride over the etched opening surfaces, such as via openings and trench line openings, removing excess barrier layer from the wafer surface according to CMP, depositing a metal seed layer, for example by electro deposition , preferably copper, over the barrier layer, and then electroplating a metal, for example copper, over the seed layer to fill the etched features to form, for example, vias and trench lines. Finally, the deposited layers and the dielectric layers are planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Metal electroplating in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The plating surface is contacted with an electrical power source forming the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the plating surface. Alternatively, spontaneous electrodeposition without an applied potential can occur if thermodynamically favorable conditions exist with respect to the substrate and electroplating solution which are conducive to spontaneous electrodeposition (electroless plating).
One problem with the prior art damascene formation process including electrodeposition methods include the incomplete coverage of the barrier layers, for example, tantalum nitride and titanium nitride. Barrier layers are used to cover the walls and bottoms of semiconductor features, such as damascene structures, to prevent the diffusion of copper into surrounding insulating layer, for example low dielectric porous oxides. As device sizes shrink and aspect ratios increase, coverage of conformal layers including barrier layers by PVD and CVD is increasingly problematical, often leaving uncovered areas, for example, near the upper surfaces of trench lines. In addition, a capping layer such as silicon carbide and metal nitrides such as, silicon nitride, or silicon oxynitride are typically formed over the metal filled damascene structure in order to prevent copper diffusion into overlying insulating layers. A shortcoming of these capping layers is that they typically have relatively high dielectric constants (e.g.,  greater than 6.5) thereby increasing the overall average dielectric constant, and signal delay time constants of the multilayer semiconductor device. Another shortcoming includes poor adhesion between the capping layer and porous low-k dielectric insulating layer, frequently resulting in peeling of layers when subjected to, for example, CMP induced stresses.
There is therefore a need in the semiconductor processing art to develop a method whereby a protective capping layer may be applied to protect surrounding materials from copper diffusion while minimizing contributions to the overall dielectric constant.
It is therefore an object of the invention to provide a method whereby a protective capping layer may be applied to protect surrounding materials from copper diffusion while minimizing contributions to the overall dielectric constant.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a self-aligned capping layer over a metal filled feature in a multi-layer semiconductor device.
In a first embodiment according to the present invention, the method includes providing an anisotropically etched feature included in a substrate; blanket depositing a first barrier layer over the anisotropically etched feature to prevent diffusion of a metal species into the substrate; filling the anisotropically etched feature with a metal to form a metal filled feature substantially filled with metal; and, planarizing the substrate surface to include forming an exposed surface of the metal filled feature; and, selectively depositing a second barrier layer to cover the exposed surface of the metal filled feature to form a capping layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.